1. Field of the Invention
The present invention relates to the implementation of a capacitor in a multiple layer integrated circuit. The present invention more specifically applies to compound integrated circuits including a digital part and an analog part.
2. Discussion of the Related Art
In a compound integrated circuit in CMOS technology, MOS transistors are generally distributed in distinct blocks according to whether they belong to the analog or digital parts of the circuit. The analog and digital blocks are generally supplied separately from each other, that is, by means of different leads of the integrated circuit.
In an HCMOS technology with several metal layers, a capacitor is generally made between the lower metallization level and the level immediately above. To reduce the surface bulk of the capacitor, a capacitor is generally made by assembly of two symmetrical capacitors on either side of a lower metal layer portion.
FIG. 1 very schematically shows a conventional embodiment of a capacitor in HCMOS technology with several metal layers. Above a P-type substrate 1, in which are formed the MOS transistors, the successive deposition and etching of a polysilicon layer 2 and of several metal layers 3, 4 are provided. A second polysilicon layer may be provided. Each layer is separated from the two neighboring layers by a dielectric layer, generally made of silicon oxide.
In the present invention, "metallization level" is meant to refer to a polysilicon layer or to a metal layer.
In FIG. 1, the capacitor is formed of two intermetallic capacitors C1, C2, respectively between layers 3, 4, and 2, 3. A first terminal 6 of the capacitor is formed of a pad that contacts intermediary layer 3. A second terminal 7 of the capacitor is formed of a contact pad connected to layers 2 and 4, so that capacitors C1 and C2 are in parallel. Other levels are generally provided above level 4, for example, at least one metal layer 5 which is used to form the tracks of connection of the different components to a positive supply potential Vdd. Substrate 1 is at a potential Vss, generally the ground.
Stray capacitances Cp, C'p are respectively present between layer 2 and substrate 1, and between the track of connection of terminal 6 to layer 3 and substrate 1. Similarly, if the etch pattern of layer 5 (or of any other higher metallization level) causes this layer to be present above the implemented capacitor, stray capacitances (not shown) appear between layer 4 and layer 5, and between the connection of terminal 6 to layer 3 and layer 5.
FIG. 2 shows the equivalent schematic electric diagram of capacitor C thus made between terminals 6 and 7. For clarity, only stray capacitances Cp, C'p have been taken into account, on the side of substrate 1.
A problem which arises in the circuit operation is that the charge of capacitor C can be corrupted or changed by noise crossing capacitances Cp, C'p. This problem is particularly critical in compound circuits due to the switching noise from the digital part of the circuit which corrupts the ground and transits through substrate 1 to above the capacitor.
The importance of this problem depends on the signal-to-noise ratio desired for the capacitor, and thus on the importance of the charge level of this capacitor. The lower the charge level to be stored by the capacitor, the greater the influence of switching noise.
It should be noted that the same problem arises for any intermetallic storage capacitor, the charge level of which is not negligible with respect to the switching noise.